1. Field of the Invention
The present invention relates generally to stacked capacitors, and more particularly to forming multiple stacked capacitors within a relatively large opening with thick capacitor dielectric.
2. Description of the Related Art
Capacitors are widely used for storing data by charge retention, as known to one of ordinary skill in the art. For example, a DRAM (dynamic random access memory) cell and a ferroelectric memory cell each use a capacitor for such data storage.
Integrated circuits are desired to be fabricated ever more densely. On the other hand, the capacitance of an integrated circuit capacitor decreases with size reduction of the capacitor. Such lower capacitance degrades the sensing margin during read of data stored in a memory cell.
Thus, the capacitance of the capacitor is desired to be increased for smaller area of the capacitor. To that end, the dielectric constant of the capacitor dielectric between two electrodes is increased for in turn increasing the capacitance. Alternatively, a stacked capacitor is formed with increased overlap between two electrodes formed with increased height for increased capacitance.
One example of such a stacked capacitor is disclosed in U.S. Pat. No. 6,559,497 as illustrated in the cross-sectional view of FIG. 1. Referring to FIG. 1, a first oxide layer 11 is formed on a semiconductor substrate 10. A conductive plug 12 is formed through the first oxide layer 11 to contact a predetermined region of the semiconductor substrate 10.
In addition, a second oxide layer 13 is formed to cover the first oxide layer 11 and the conductive plug 12. A hole 14 is formed through the second oxide layer 13 to expose the conductive plug 12. A conformal lower electrode 15 is disposed on inner sidewalls and a bottom surface of the hole 14. A conformal capacitor dielectric 16 covers the lower electrode 15. An upper electrode 17 is disposed on the capacitor dielectric and fills the hole 14. The upper and lower electrodes 15 and 17 and the capacitor dielectric 16 form the stacked capacitor.
In the prior art stacked capacitor of FIG. 1, the lower electrode 15 is conformally deposited onto the inner sidewall(s) and the bottom wall of the hole 14 for increasing the area of overlap between the electrodes 15 and 17. In addition, the capacitor dielectric 16 is a high-k dielectric (i.e., a dielectric having a dielectric constant higher than that of silicon dioxide SiO2). Such increased area of overlap and such a high-k capacitor dielectric 16 increase the capacitance of the stacked capacitor.
However, as integrated circuits are fabricated more densely, the aspect ratio of the hole 14 is increased. For ensuring that the upper electrode 17 properly fills the hole 14 without a void, the lower electrode 15 and the capacitor dielectric 16 are formed to be as thin as possible. For example, the total thickness of the lower electrode 15 and the capacitor dielectric 16 is smaller than half of the width of the hole 14 for ensuring that the upper electrode 17 properly fills the hole 14.
With such a thin capacitor dielectric 16, leakage current between the electrodes 15 and 17 may increase, for degradation of data stored in the capacitor. On the other hand, with a thicker capacitor dielectric 16, the upper electrode 17 may not properly fill the hole 14 with void formation leading to decreased overlap and in turn decreased capacitance between the two electrodes 15 and 17.
In addition, the capacitor dielectric 16 may be comprised of a ferroelectric material as disclosed in U.S. Pat. No. 6,559,497. As known to one of ordinary skill in the art, a ferroelectric material is polarized to a predetermined direction according to the intensity and direction of an external electric field. Furthermore, a hysteresis phenomenon maintains the polarized state of the ferroelectric material even after the external electric field is removed. Thus, a ferroelectric memory device with the ferroelectric material has a nonvolatile characteristic from the polarization hysteresis for maintaining stored data even when power is cut off.
However, if the thickness of the capacitor dielectric 16 comprised of a ferroelectric material is reduced, the polarization hysteresis of the capacitor dielectric 16 may be deteriorated. For example, if the thickness of the capacitor dielectric 16 is less than about 500 Å, the capacitor dielectric 16 may not maintain the polarization hysteresis. In that case, a ferroelectric memory device formed with the stacked capacitor loses the nonvolatile characteristic.
Nevertheless, the width of the hole 14 and thus the thickness of the capacitor dielectric 16 of the prior art stacked capacitor of FIG. 1 is desired to be further decreased for higher integrated circuit density. Such decreased thickness of the capacitor dielectric 16 deteriorates reliability of the semiconductor device formed with the stacked capacitor of FIG. 1.
Thus, a mechanism is desired for forming stacked capacitors with a larger thickness of the capacitor dielectric even in densely fabricated integrated circuits.